A Phase-Locked Minimum-Energy-Point-Tracking Enabled by Unified-Clock-Power-and-Body-Bias Slack Regulation and PI-Ratio Based In-Situ Loop Gain Optimization with 97.4% Supply Voltage Margin Recovery at Minimum-Energy-Point in 28nm FDSOI
Energy efficiency is a primary goal in modern digital system design, especially as IoT, mobile, and AI applications demand low power consumption alongside high performance. To optimize energy consumption, both supply voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>) and threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) need to be tuned to operate at the Minimum Energy Point (MEP), where dynamic energy (E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dyn</inf>) and leakage energy (E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">leak</inf>) are optimally balanced[1]. Achieving MEP under varied environmental and workload conditions is essential for sustaining energy-efficient performance across diverse applications, driving the need for Minimum Energy Point Tracking (MEPT) mechanisms [2]–[6].
Authors
- Hyungmin Gi (ORCID: https://orcid.org/0000-0002-6851-2825)
- Seonho Kim
- Yoonmyung Lee (ORCID: https://orcid.org/0000-0001-9468-1692)
- Donguk Seo (ORCID: https://orcid.org/0000-0003-3453-3940)
- Yeohoon Yoon (ORCID: https://orcid.org/0000-0002-1198-3992)
- Shin Han
- Minhyeok Jeong (ORCID: https://orcid.org/0000-0002-2276-4197)
- Sungyong Park (ORCID: https://orcid.org/0009-0002-8756-4994)
- Minsik Cho (ORCID: https://orcid.org/0000-0002-9307-8549)
- W. H. Lee
- Jongmin Lee (ORCID: https://orcid.org/0000-0002-7084-5530)
- Mingyu Kim
- Donggyu Kim (ORCID: https://orcid.org/0009-0003-5156-2919)
Institutions
- Samsung (South Korea) (KR)
- Hyundai Motors (South Korea) (KR)
- Ajou University (KR)
- Sungkyunkwan University (KR)
Publication Details
- Published
- 2025-04-13
- DOI
- https://doi.org/10.1109/cicc63670.2025.10983658
- Citations
- 1
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.73