A 133.6-µW 1kHz-BW Multi-Bit 2nd-Order Incremental ADC Achieving 115.4-dB SNDR with Low-Cost Coarse-Sorting DEM and Zip-Extended-Counting

Incremental ADCs (IADCs) are gaining popularity in sensor interfaces and instrumentation applications for their ability to achieve both high resolution and multiplexing-friendly Nyquist-rate conversion [1]. To improve resolution and bandwidth in an energy-efficient manner, high-order and multi-bit methods are commonly employed in IADCs. However, element mismatch in multi-bit DACs can directly impair the IADC linearity. For free-running Delta-Sigma ADCs, dynamic element matching (DEM) techniques such as data weighted averaging (DWA), are potential solutions. Unfortunately, the effectiveness of these methods has been degraded due to the non-uniform weighting in high-order IADCs [2], which places limitations on achieving high SNDR. In [3], a Smart-DEM algorithm was proposed to dynamically and serially cancel out elements' mismatch based on the weights. However, the Smart-DEM operates with a high-speed clock (N<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> x Fs), where N is the number of elements, and its hardware complexity grows logarithmically with the oversampling rate (OSR), leading to significant hardware and power consumption overhead.