A Timing-Robust 10b 13GS/s ADC with Analog Fourier Transform Based Frequency Interleaving

Gigahertz high-speed ADCs are highly demanded with the development of high-speed wireless, wireline and optical communication applications, where the time-interleaved architecture is commonly used with few other options. Time-interleaved ADCs, on the other hand, suffers from mismatch and timing errors among the interleaving channels. The timing errors, including sampling jitter, clock skew and bandwidth mismatch, are the fundamental limiting factor and increasingly difficult to be dealt with, especially for sampling rates up to tens to hundreds GHz, resulting in significant amount of design effort, complexity, and overhead in power and area. Historically, hybrid filter banks (HFB) were proposed to reduce the timing-error sensitivity by dividing the frequency information into multiple segments and transferring them into baseband [1]. However, the increased power and complexity have made the option impractical. The Fourier transform (FT), as the mathematical foundation of the frequency-domain analysis, performs an inherent frequency division and has been explored for channelization in the receiver front-end [2] as well as ADC [3], this characteristic makes analog Fourier transform (AFT) and frequency interleaving particularly relevant and beneficial. Analysis has shown the FT has the potential in improving timing-error robustness structurally for a high-speed sampling system [4]. However, conventional AFT is extremely complicated considering the irrational coefficient matrix and extensive clock control, mismatch and driving difficulties. As a result, there has not been a frequency interleaved ADC showing competitive performance and/or energy efficiency as compared to time-interleaved ADCs.