A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel

The 5G communication using 24.25-29.5 and 37-43.5 GHz millimeter-wave bands requires agile local oscillators with at least 19.5% and 16.1 % frequency tuning range (FTR). A significant difficulty of PLL frequency hopping across a wide frequency range is the tuning nonlinearity of the VCO (or DCO), and the nonlinearity is more serious with a large FTR. The Adaptive Frequency Switching in [1] estimates the next oscillator tuning word (OTW) by linear extrapolation. The type-I loop in [2] assumes linear tuning to obtain the transfer function, and achieves sub-60-ns searching for coarse OTW with an 11.4%-FTR VCO. A similar type-I loop was presented in [3]. The binary search FLL in [4] is independent on nonlinearity with a large FTR but completely abandons a priori knowledge about the tuning curve, which may worsen the hopping time. Another problem is the initial phase error of the phase locking process. The phase alignment methods so far [3] [4] are based on adjusting the divider or choosing a proper VCO cycle. The phase cancellation in [3] achieves below TDC resolution after many reference cycles. However, in one reference cycle, the phase error cannot be further reduced than one VCO cycle [4]. Integrated jitter is another important metric for local oscillators to support wide-band high-order modulation. Though sub-50-fs jitter metrics are reported in [4] [5], these experiments are based on typical fractional-N channel with out-of-band fractional spurs. The near-integer fractional-N jitter is more solid to evaluate the fractional-N PLLs and prior arts [6]–[9] show around 60-fs jitter. While the SiGe PLL in [10] shows 45-fs jitter with 2100-mW power consumption, there is seldom CMOS PLL achieving sub-50-fs jitter.