UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies
UCle is a new chiplet interconnect standard offering superior bandwidth density and interoperability. This paper provides a comprehensive exploration of UCle interconnect design, focusing on four essential aspects: interface circuit architecture, floorplan strategies, package-level channel optimization, and power delivery network (PDN) analysis. The insights presented offer a systematic approach to design UCle-compliant interfaces, considering various packaging options and link speeds to achieve the best-fit design.
Authors
- Shenggao Li (ORCID: https://orcid.org/0000-0001-9296-1121)
- Wei‐Chih Chen (ORCID: https://orcid.org/0000-0003-4172-5529)
- Hsin‐Hung Kuo (ORCID: https://orcid.org/0000-0002-4245-2262)
- Mu-Shan Lin (ORCID: https://orcid.org/0000-0002-1268-1013)
- Chien-Chun Tsai
- Yu‐Jie Huang (ORCID: https://orcid.org/0009-0006-8684-5785)
- Shu-Chun Yang (ORCID: https://orcid.org/0009-0004-6496-7795)
Institutions
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Published
- 2025-04-13
- DOI
- https://doi.org/10.1109/cicc63670.2025.10983497
- Citations
- 2
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 1.46