Real-Time Fault Detection, Classification and Location in Power Distribution Systems Using D-PMU Enabled Hardware-in-the-Loop Testbed

This paper presents a real-time hardware-in-the-loop (HIL) testbed designed for fault detection, classification, and location (FDCL) in power distribution systems, utilizing Distribution Phasor Measurement Units (D-PMUs) and the OPAL-RT simulator. The testbed integrates D-PMUs and the OPAL-RT platform to generate time-synchronized measurements at strategic locations within a medium voltage (MV) grid. The FDCL algorithm leverages these measurements along with a digital twin model of the grid to enhance fault management capabilities. The algorithm uses the D-PMUs data to accurately identify faulted areas and estimate fault locations, regardless of fault type, grid topology, or grounding system. A series of test cases, involving various fault types, resistances, and locations, were conducted to validate the performance of the FDCL system. Results demonstrate the algorithm's efficacy in quickly and accurately identifying and locating faults, thus minimizing outage durations and improving grid reliability.