A Resistive Dynamic Bias Comparator with Flying Capacitors Achieving 129µVrms Input-Referred Noise at 1GS/s in 28nm FD-SOI

Comparators play a key role in converting analog signals into the digital domain. For instance, in SAR ADCs, a high performance comparator is necessary to achieve both high sampling rate and high resolution. Typically, the pre-amplifier of the comparator is crucial to achieve low input-referred noise, small CLK-Q delay, and high energy efficiency. A dynamic pre-amplifier based on a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{G}_{\mathrm{m}}-\mathrm{C}$</tex> amplifier can operate at moderate speed while achieving good energy efficiency [1]–[3]. However, the limited swing to discharge the output voltage before the comparator decision makes it difficult to design for low noise. A floating inverter amplifier (FIA) [4] and its derivatives [5]–[6] can achieve very low noise, but must drive the large load capacitor to an appropriate level, resulting in a low speed. High-speed comparators with GS/s have been demonstrated only with moderate noise levels and low energy efficiency [7]. This work presents a dynamic comparator using a resistive dynamic bias pre-amplifier with flying capacitors. It breaks the inherent trade-off between the operating speed and noise, achieving a small CLK-Q delay of 0.39ns and an low input-referred noise of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$129\mu \mathrm{V}_{\text{rms}}$</tex>, simultaneously. It exhibits the lowest input-referred noise at an operating speed exceeding 1GS/s, and also shows low VCM sensitivity to the input-referred noise and CLK-Q delay.