A 16-bit Incremental ADC Enabled by An Efficient Shooting Integrator with Inherent Noise Reduction

Switched-capacitor (SC) integrator is a versatile circuit used exten-sively in filter and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> modulator design. In high-resolution discrete-time <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> data converters, their integrators often consume most of the power to meet the noise and speed requirements. Recent ad-vancements have focused on replacing traditional operational ampli-fiers (op-amps) in integrators with more efficient alternatives, such as dynamic amplifiers, ring amplifiers [1], floating inverter amplifiers [2], etc. Despite these advancements, the fundamental tradeoff be-tween noise, power, speed, and accuracy remains in SC integrators. Among the prior integrator designs shown in Fig. 1, using a virtual ground reference buffer can reduce the integrator's capacitive load to achieve power saving [3], while noise and nonlinearity introduced by the buffer become problematic. Zero-crossing-based (ZCB) integra-tor can isolate its capacitive load from the driving circuit [4]. However, its large settling error induced by comparator delay restricts their use primarily in moderate-resolution systems. Integrators with capacitor stacking and buffering inherit the efficiency of passive integrators [5], while they can only handle small inputs.