W-Band Power Amplifier With Reconfigurable Output Matching Network

This paper presents an on-chip load-reconfigurable three-stage MMIC power amplifier (PA) in a 40-nm GaN process. A staging ratio of 1: 2: 4 is used for two drive stages and an output reactively power-combined stage. The output part of the matching network following the combiner is a discrete reconfigurable impedance matching network that uses two shunt <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 37.5 \mu\ \mathrm{m}$</tex> HEMTs. The tunability is achieved by changing the gate bias voltage of the devices between 3 states. The reconfigurable network enhances efficiency and output power of the PA as the load impedance is varied from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\vert\Gamma\vert=[0-0.8]$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\angle \Gamma$</tex> from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$[0-360^{\circ}]$</tex>. The PA small-signal measurements show a peak gain of 18.1 dB at 77 GHz. For an input power of 11 dBm, the output power is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$25\ \text{dBm}(0.3\ \mathrm{W}$</tex>), with a large-signal gain of 13 dB and power-added efficiency of 10 % at 77.2 GHz.