Area-Efficient UWB CMOS Power Amplifier with Hybrid Trifilar

This paper designs a wide-band (WB) power amplifier (PA) fabricated in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18 \mu\ \mathrm{m}$</tex> CMOS process. The PA uses three cascaded inductive peaking amplifiers with a resistor in series with an inductor as the amplifier load. The sub-amplifiers use three load-on-chip inductors compacted in the same area to form two pairs of orthogonal transformers to reduce chip area. At 6.5 GHz, the power gain <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> is 19.06 dB; at 8 GHz, the power gain <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> is 17.18 dB. The fabricated PA with the trifilar occupies an area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.88 \times 0.74\ \text{mm}^{2}$</tex> including the input/output pads. Two design techniques are used in the UWB PA for low die area: (a) a lowcoupling orthogonal transformer, and (b) a coupling transformer in series with resistors. The three inductors form a trifilar with coupling and small coupling coefficients.