A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback

Level-crossing (LC) ADCs are superior choices for digitizing sparse input signals, which have short bursts of activity followed by long periods of silence. Monitored by a continuous-time (CT) comparator, the input signal is only processed after crossing a predefined voltage. This event-driven working scheme results in concentrated conversions solely during active periods, significantly reducing power consumption in sparse signal processing and demonstrating notable advantages in data compression applications. However, the resolution of LC ADCs is limited due to the inherent signal-dependent delay error between the crossed moment and the detected time. Among prior works, the highest reported SNDR is 64dB when the third harmonic falls within the bandwidth [1]–[9]. This work presents the first LC pipelined ADC capable of accurately extracting and finely quantizing the signal-dependent error, thereby improving the resolution of LC ADCs. The proposed ADC achieves a 72.5dB peak SNDR and consumes 1.2µW (static) −11.8µW (with full-bandwidth input), corresponding to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{W}}$</tex> of 9-86fJ/conv.step and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{S}}$</tex> of 164.8dB (Since the power consumption of LC ADC varies with input frequency, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{S}}$</tex> of LC ADCs is calculated using the peak SNDR including the third harmonic and the maximum power consumption).