A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager

Edge AI devices need to be energy-efficient and compact while maintaining sufficient accuracy. Compute-in-memory (CIM) is a promising approach to achieve energy-efficient multiply-and-accumulate (MAC) operations. Analog CIMs (ACIMs) [1]–[5] generally offer higher energy efficiency but are sensitive to PVT variations, while digital CIMs (DCIMs) [6], [7] provide accurate computations but with mediocre energy efficiency. Combining analog and digital computing can help balance accuracy with power and area overheads. However, designing an energy-efficient hybrid CIM faces multiple challenges, as shown in Fig. 1. First, prior hybrid CIMs [8]–[10] still exhibit restricted efficiency due to their inherent bit -wise hybrid (BWH) structure, for example, accurate computation to the ‘0’ value of most significant bits (MSBs) wastes energy. Second, DRAM-CIM [4], [5] typically demonstrates higher efficiency compared to SRAM-CIM [1]–[3], but it necessitates frequent off-macro refreshes, leading to additional system power and latency. Third, high bit-sparsity (>90%) in MSBs can significantly cause redundant MAC and quantization power.