Forward Error Correction Requirements for Data Center Connectivity

Training today's complex AI models, such as transformers, requires the use of distributed compute platforms within data centers involving coordinated execution across thousands of GPUs [1]. The connectivity between these compute sockets needs to support high data rates, incur low latency, and be energy efficient to ensure that the time-to-accuracy during training is minimized. Forward error correction (FEC) is a critical enabler of data center connectivity due to its ability to relax the SNR requirements on the analog front-end, thereby enabling signaling rates in the 100s of GBaud. However, the impact and role of FEC to support a high-performance distributed compute fabric is not well understood. This paper makes three contributions: 1) it derives specifications on FEC for connectivity; 2) it hypothesizes that binary BCH codes are an excellent baseline FEC for connectivity; and 3) it validates this hypothesis via the design of a BCH(255, 207) decoder in 16nm FinFET.