A CMOS LNA with Improved Multi-Path Noise-Canceling for K-Band Communications

This paper presents a transformer-based improved multi-path noise-canceling (IMNC) low noise amplifier (LNA) for K-band satellite communications. The design enhances the dual-path noise cancellation and significantly reduces the noise figure. The proposed LNA employs a three-coil transformer with dual-eight-shaped inductor to boost gain, and introduces a noise cancellation path for the common-gate transistor to optimizes noise performance. During the circuit design phase, a multicomponent integrated modeling (MIM) technique is applied, which accurately characterizes the EM field of the LNA and ensures high consistency between simulation and measurement results. The LNA, fabricated in a 40 nm CMOS process, consumes 28.8 mW of power and achieves a peak gain of 12.6 dB. Its 3-dB bandwidth ranges from 19.9 to 25 GHz with a minimum noise figure of 2 dB. The core area of the LNA is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.16 ~\text{mm}^{2}$</tex>.

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Publication Details

Published
2025-04-14
DOI
https://doi.org/10.1109/wamicon64429.2025.11004111
Citations
2
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
1.46
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article

A CMOS LNA with Improved Multi-Path Noise-Canceling for K-Band Communications

Leilei Huang, Chunqi Shi, Runxi Zhang, Jinghong Chen et al.
2 citations
Radio Frequency Integrated Circuit Design
1.46
article

A CMOS LNA with Improved Multi-Path Noise-Canceling for K-Band Communications

Leilei Huang, Chunqi Shi, Runxi Zhang, Jinghong Chen, Ziyao Wang, C. H. Hu
article en
2 citations

Abstract

This paper presents a transformer-based improved multi-path noise-canceling (IMNC) low noise amplifier (LNA) for K-band satellite communications. The design enhances the dual-path noise cancellation and significantly reduces the noise figure. The proposed LNA employs a three-coil transformer with dual-eight-shaped inductor to boost gain, and introduces a noise cancellation path for the common-gate transistor to optimizes noise performance. During the circuit design phase, a multicomponent integrated modeling (MIM) technique is applied, which accurately characterizes the EM field of the LNA and ensures high consistency between simulation and measurement results. The LNA, fabricated in a 40 nm CMOS process, consumes 28.8 mW of power and achieves a peak gain of 12.6 dB. Its 3-dB bandwidth ranges from 19.9 to 25 GHz with a minimum noise figure of 2 dB. The core area of the LNA is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.16 ~\text{mm}^{2}$</tex>.

University of Houston (US), East China Normal University (CN)
Openalex Percentile: Top 17%
Radio Frequency Integrated Circuit Design
1.46
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