A Fractional-N Cascaded PLL Employing the Calibration-Free Noise-and-Spur Cancellation Technique

Fractional-N cascaded PLLs, which utilize a 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage integer loop as the reference frequency multiplier and a 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-stage fractional loop as frequency synthesizer, serve as the building block in modern wireless systems [1]–[8]. Benefitting from small layout area and easy integration, the ring oscillator (RO)-based reference frequency multiplier is widely used as the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage PLL [9], yet it invariably suffers from inferior noise and limited spur control due to their high K<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RO-VCO</inf> and susceptibility to power supply variations [10]. In this context, various approaches, including sampling PLLs, delay-locked loops, and injection-locked clock multipliers, have been explored to extend the closed-loop bandwidth of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage as well as to suppress the internal RO noise [9]–[17]. Nonetheless, the reported bandwidths are limited below fREF/2 due to the PLL stability issues, leaving the PLL phase noise (PN) impaired by the residual RO noise. Alternatively, a feed-forward noise cancellation technique has been proposed to cancel the RO noise, but it requires background calibration to adjust the feed-forward gain [18]. In this paper, we propose a cascaded PLL architecture that incorporates a calibration-free over-sampling cancellation path to cancel the noise and spurs generated in the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage RO-based PLL across all frequencies. Meanwhile, we also introduce a 4th-order LC ladder-based LC-OSC in the 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-stage that suppresses the 4th harmonic noise, achieving a FoM of 192 dBc/Hz at 10 MHz offset. Accordingly, when it is clocked by a 100 MHz reference signal, the proposed cascaded PLL achieves a 127.8 fs rms jitter and an equivalent 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(f_{\text{eq}-\text{bw}1})$</tex> exceeding <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3f_{\text{REF}}$</tex> with only a 4.48 mW power consumption, and its overall FoM reaches −251.4 dB.