A 40nm 0.05-1.4uJ/inference Sample-Wise-Adaptive Spiking Neural Network Processor with Dynamic Neuron-Pruning and Unstructured-Model-Aware Architecture

The human brain exemplifies a highly adaptive system capable of dynamically recruiting neural resources in response to varying cognitive demands [1]. It recruits a complex network with a large pool of neurons for hard samples, while it recruits a simpler network with fewer neurons for easy samples, achieving sample-wise adaptation, as shown in Fig. 1 (top left). Therefore, it can achieve optimal energy efficiency and processing latency. Recent advances in neuromorphic processors for loT exploit the event-driven feature and temporal-spatial sparsity of Spiking Neural Network (SNN), leading to promising energy efficiency, while achieving task-agnostic processing [2]–[5]. However, these works predominantly focus on task-level adaptation, overlooking the aforementioned capability of the brain for fine-grained sample-wise adaptation, which incurs substantial redundancy in computations, drastically compromising the energy efficiency, especially for frequent presences of easy samples (Fig. 1 (top right)). To deal with this issue, this paper presents a sample-wise adaptive SNN processor with dynamic neuron-pruning to reconstruct an optimized, sample-specific SNN, achieving ultra-low energy consumption and latency. Figure 1 (bottom) illustrates 3 main features of our work: (1) A dynamic pruning scheme utilizing a tiny Perception Network (PN) that identifies inference-relevant (IR) neurons and prunes inference-irrelevant ones In the Inference Network (IN) for each sample to minimize computational costs. (2) An efficient unstructured-model-aware architecture parallelly scheduling active weights for IR neurons into a pipeline-event coupled processing strategy to optimize throughput and energy efficiency. (3) A hierarchical workload monitor, structured across synapse, neuron, and layer levels, enables workload-aware clock gating to mitigate the energy overhead resulting from sample-variant workload imbalances.

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Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10983259
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

A 40nm 0.05-1.4uJ/inference Sample-Wise-Adaptive Spiking Neural Network Processor with Dynamic Neuron-Pruning and Unstructured-Model-Aware Architecture

Ziyi Yang, Zhuo Zou, Jinqiao Yang, Zikai Zhu et al.
Advanced Memory and Neural Computing
article

A 40nm 0.05-1.4uJ/inference Sample-Wise-Adaptive Spiking Neural Network Processor with Dynamic Neuron-Pruning and Unstructured-Model-Aware Architecture

Ziyi Yang, Zhuo Zou, Jinqiao Yang, Zikai Zhu, Anqin Xiao, Longrun Xv, Lirong Zhenq
article en

Abstract

The human brain exemplifies a highly adaptive system capable of dynamically recruiting neural resources in response to varying cognitive demands [1]. It recruits a complex network with a large pool of neurons for hard samples, while it recruits a simpler network with fewer neurons for easy samples, achieving sample-wise adaptation, as shown in Fig. 1 (top left). Therefore, it can achieve optimal energy efficiency and processing latency. Recent advances in neuromorphic processors for loT exploit the event-driven feature and temporal-spatial sparsity of Spiking Neural Network (SNN), leading to promising energy efficiency, while achieving task-agnostic processing [2]–[5]. However, these works predominantly focus on task-level adaptation, overlooking the aforementioned capability of the brain for fine-grained sample-wise adaptation, which incurs substantial redundancy in computations, drastically compromising the energy efficiency, especially for frequent presences of easy samples (Fig. 1 (top right)). To deal with this issue, this paper presents a sample-wise adaptive SNN processor with dynamic neuron-pruning to reconstruct an optimized, sample-specific SNN, achieving ultra-low energy consumption and latency. Figure 1 (bottom) illustrates 3 main features of our work: (1) A dynamic pruning scheme utilizing a tiny Perception Network (PN) that identifies inference-relevant (IR) neurons and prunes inference-irrelevant ones In the Inference Network (IN) for each sample to minimize computational costs. (2) An efficient unstructured-model-aware architecture parallelly scheduling active weights for IR neurons into a pipeline-event coupled processing strategy to optimize throughput and energy efficiency. (3) A hierarchical workload monitor, structured across synapse, neuron, and layer levels, enables workload-aware clock gating to mitigate the energy overhead resulting from sample-variant workload imbalances.

Fudan University (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 91%
Advanced Memory and Neural Computing
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