A 0.16mm²450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques

ADCs with a wide BW over 450MHz and 70dB DR are in high demand for communication applications, where continuous-time pipeline (CTP) ADC can be a power-efficient candidate from a system perspective [1]. However, CTP still faces two major challenges in practice: area consumption and component value variation. For larger input and higher DR, prior CTP works [1], [2] use an LC lattice to achieve accurate in-band delay alignment between the signal path and quantization path, suffering from a large inductor area (0.45mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in [2]). Works [3], [4] use RC all-pass filter (APF) as an alternative, but it suffers from inaccurate in-band delay alignment, leading to large input signal leakage. With an RC APF, the magnitude of the leakage with OSR around 4 is equivalent to the quantization error of a 4-bit quantizer, which limits the input magnitude and overall DR of CTP. The sub-ADC-DAC time-interleaving technique is adopted in [5] to attenuate the residue magnitude, but it costs large power and area. The other practical challenge is the process and temperature variations of passive components (R/L/C ). Even small RC/LC variation (e.g., ±10%) can cause large delay misalignment and severe leakage, resulting in potential saturation and degraded DR. Therefore, meticulous RC/LC tuning is required in all CTP stages in prior works [1]–[5], which is a high implementation overhead.