A 90.1dB SNDR, 180.2dB FoM_SNDR, 10kHz BW Gm-C-based Δ Σ. ADC with Capacitive Input Feedforward and Duty-Cycled Gm Technique

The growing interest in the Internet of Things (loT), wireless biomedical devices, and edge computing has substantially increased the demand for ADCs with ~khz bandwidth and high resolution (>80dB SNDR) [1]–[9]. Given the stringent power budgets in these applications, the ADCs must has low power consumption below 10 µW. In addition, the ADCs need to be easy to drive to relax the required driving capability of the input buffer, thereby lowering its power consumption. Continuous-time (CT) <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Lambda\Sigma$</tex> ADCs are the preferred choice for meeting these specifications, as their oversampling and noise-shaping nature enable precise quantization of the signal of interest. In addition, the CT input inherently provides anti-aliasing and is free from kT/C noise, which simplifies input buffer design and contributes to improving system-level energy efficiency [10]–[12]. In response to this demand, we present a low-distortion Gm-C-based <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \mathrm{I}$</tex> ADC that achieves a 90.1dB SNDR within a 10kHz bandwidth with 9.7µW power consumption. This results in an SNDR Schreier figure of merit (FoM) of 180.2dB, underscoring its superior energy efficiency. The exceptional performance is primarily attributed to two key innovations: capacitive input feedforward (FF) and duty-cycled Gm technique. To the best of our knowledge, this is the first implementation of capacitive input FF in an open-loop integrator-based CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> ADC.