A CMOS <i>E</i>-Band Reconfigurable Series Doherty Power Amplifier for 6-/12-dB Back-Off Efficiency Enhancement

This letter presents a reconfigurable series Doherty power amplifier (PA) that supports dual-mode operation with 6- and 12-dB power back-off (PBO) by adjusting the dc bias voltages of the sub-PAs. As a proof of concept, a prototype PA operating in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i>-band was fabricated using 40-nm CMOS technology. The PA exhibits a measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$</tex-math> </inline-formula> of 15.2–16.5 dBm and a peak power-added efficiency (PAE) of 13.5%–16.4% across 72–82 GHz. In Mode-1, it demonstrates a 6-dB back-off PAE of 8.7%–11.7%. In Mode-2, it achieves a 12-dB back-off PAE of 5.2%–7.5%, providing a maximum efficiency enhancement of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.84\times $</tex-math> </inline-formula> over an ideal Class-B PA. For a 6-Gb/s 64-QAM signal, the PA delivers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {avg}}$</tex-math> </inline-formula> of 8.9/8.8 dBm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {PAE}_{\text {avg}}$</tex-math> </inline-formula> of 9.0%/9.8% with an error vector magnitude (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {EVM}_{\text {rms}}$</tex-math> </inline-formula>) of −25.4/−24.8 dB in Mode-1/Mode-2, respectively.