An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator

Loop closure detection (LCD) is crucial in LiDAR-based Simultaneous Localization and Mapping (SLAM) for smart vehicles, demanding both real-time performance and high-accuracy. Unfortunately, although the state-of-the-art LCD algorithms offer high-accuracy, the large search space in clustering, the high complexity in descriptor computation, and the slow speed in retrieval prevent them from achieving real-time performance. To address the issue, we propose three key techniques to achieve a real-time FPGA-based LCD framework. First, we reduce the clustering time by designing a Range Image-based clustering accelerator that significantly reduces the search space and achieves high-parallelism. Second, we reduce the descriptor computation time by designing an accelerator that selects only high-quality features and employs simplified operations to achieve low complexity. Third, we reduce the retrieval time by proposing a novel dual-descriptor cross-verification mechanism that uses fewer descriptors while maintaining high-accuracy. Compared to the state-of-the-art, experimental results show that our LCD accelerator demonstrates 128.8x performance improvement across multiple datasets in various scenes and achieves the required real-time performance.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-05-19
DOI
https://doi.org/10.1109/tcsi.2025.3567058
Citations
1
Primary Topic
Real-time simulation and control systems
Type
article
Field-Weighted Citation Impact
1.21

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An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator

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article

An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator

Jin-Jie Huang, Qi Deng, Hao Sun, Weixiong Jiang, Yajun Ha, Shuangyu Meng
article en
1 citations

Abstract

Loop closure detection (LCD) is crucial in LiDAR-based Simultaneous Localization and Mapping (SLAM) for smart vehicles, demanding both real-time performance and high-accuracy. Unfortunately, although the state-of-the-art LCD algorithms offer high-accuracy, the large search space in clustering, the high complexity in descriptor computation, and the slow speed in retrieval prevent them from achieving real-time performance. To address the issue, we propose three key techniques to achieve a real-time FPGA-based LCD framework. First, we reduce the clustering time by designing a Range Image-based clustering accelerator that significantly reduces the search space and achieves high-parallelism. Second, we reduce the descriptor computation time by designing an accelerator that selects only high-quality features and employs simplified operations to achieve low complexity. Third, we reduce the retrieval time by proposing a novel dual-descriptor cross-verification mechanism that uses fewer descriptors while maintaining high-accuracy. Compared to the state-of-the-art, experimental results show that our LCD accelerator demonstrates 128.8x performance improvement across multiple datasets in various scenes and achieves the required real-time performance.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 72(11)
ShanghaiTech University (CN), Shanghai Advanced Research Institute (CN), Southeast University (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 21%
Real-time simulation and control systems
1.21
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