Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization

As Cu interconnects near their physical limits with continued technology scaling, carbon nanotube (CNT) interconnects have emerged as a promising alternative due to their excellent conductivity. However, fabrication immaturity introduces significant process variations, causing discrepancies between ideal and actual performance. This article presents a novel approach to optimize CNT interconnects considering process variations. We first develop a parameterized CNT interconnect model that accounts for process variations. Using this model, a Bayesian Neural Network (BNN) is proposed to predict performance distributions by leveraging its inherent uncertainty. We then introduce a Bayesian optimization framework that uses the BNN’s posterior to jointly optimize interconnect parameters and buffer insertion, targeting Area-Delay Product (ADPIn this work, we use area-delay product ziegler2001optimal as the performance metric, though other metrics can also be applied within our framework.) with process variations. Experimental results demonstrate the effectiveness of our approach. The proposed BNN model achieves over 95% prediction accuracy for interconnects performance distributions. Compared to existing methods, our method achieves an average ADP improvement of 20.3% over the state-of-the-art methods and 13% over the standard Monte Carlo method. Compared with Monte Carlo method, our method also achieves an average 8.8x acceleration. Moreover, the optimized CNT interconnects show an average improvement of 82.8% in ADP and 68.7% in delay compared to Cu interconnects. This work offers an effective method for optimizing CNT interconnects under process variations and highlights their potential as a viable alternative to Cu interconnects in future integrated circuits.

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Publication Details

Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Published
2025-05-19
DOI
https://doi.org/10.1109/tcad.2025.3571336
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
0.00

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article

Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization

Zhelong Wang, Wei Xing, Yuanqing Cheng, Ning Xu
1 links
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power high-performance VLSI design
article

Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization

Zhelong Wang, Wei Xing, Yuanqing Cheng, Ning Xu
article en

Abstract

As Cu interconnects near their physical limits with continued technology scaling, carbon nanotube (CNT) interconnects have emerged as a promising alternative due to their excellent conductivity. However, fabrication immaturity introduces significant process variations, causing discrepancies between ideal and actual performance. This article presents a novel approach to optimize CNT interconnects considering process variations. We first develop a parameterized CNT interconnect model that accounts for process variations. Using this model, a Bayesian Neural Network (BNN) is proposed to predict performance distributions by leveraging its inherent uncertainty. We then introduce a Bayesian optimization framework that uses the BNN’s posterior to jointly optimize interconnect parameters and buffer insertion, targeting Area-Delay Product (ADPIn this work, we use area-delay product ziegler2001optimal as the performance metric, though other metrics can also be applied within our framework.) with process variations. Experimental results demonstrate the effectiveness of our approach. The proposed BNN model achieves over 95% prediction accuracy for interconnects performance distributions. Compared to existing methods, our method achieves an average ADP improvement of 20.3% over the state-of-the-art methods and 13% over the standard Monte Carlo method. Compared with Monte Carlo method, our method also achieves an average 8.8x acceleration. Moreover, the optimized CNT interconnects show an average improvement of 82.8% in ADP and 68.7% in delay compared to Cu interconnects. This work offers an effective method for optimizing CNT interconnects under process variations and highlights their potential as a viable alternative to Cu interconnects in future integrated circuits.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsVol. 44(12)
Wuhan University of Technology (CN), Beihang University (CN), University of Sheffield (GB)
Beijing Municipal Natural Science Foundation
Openalex Percentile: Top 91%
Low-power high-performance VLSI design
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