Hardware/Software Co-Design of Multi-Level Edge Detector on Low-Cost FPGA-Based Embedded Heterogeneous Architecture

Edge detection is a fundamental aspect of computer vision, facilitating the extraction of crucial features such as corners, edges, and line segments, which are vital for Visual Odometry-based applications. While adding more stages to an edge detector can enhance feature precision, it also increases time consumption and resource requirements, necessitating hardware optimizations. To address these challenges, this paper presents a hardware/software co-design for an efficient pipeline implementation of a Multi-level Edge Detector (MED) on a low-cost FPGA-based heterogeneous architecture. Leveraging this framework, we developed cascading duplicate shift registers based on the Single-Task (ST) mode of OpenCL, which achieves an efficient pipeline execution model for conventional cascade filters. Our ST implementation of the MED significantly outperforms the traditional NDRange implementation in both execution time and resource utilization on the targeted FPGA platform. This allows for effective deployment on the low-cost embedded DE1-SoC, with results validated through comparisons to the NVIDIA Jetson Nano GPU.