Exception Coverage on Automotive Processors

With the advent of modular and independent zonal processing in Software-Defined-Vehicles (SDV), the processor in an automotive system is expected to handle complex exception scenarios elegantly. This paper addresses the need for comprehensive exception coverage during the verification of the automotive processor. Unlike prior research focusing on only two simultaneous exceptions, our work extends to all combinations of simultaneous exceptions. The proposed methodology involves the systematic grouping of exceptions into sub-categories based on similarity while maintaining priority, followed by targeted coverage assessment for each group. A two-pass simulation technique is used to drive multiple external events like interrupts in the second pass to create high-activity time windows with simultaneous exceptions. This hierarchical approach allows for the creation of a manageable and effective exception list, facilitating thorough verification without overwhelming computational resources. Applied to a 32-bit RISC-V processor, our methodology shows a large improvement of 7X in efficiency compared to traditional methods, highlighting its advantage in enhancing safety and trustworthiness of automotive systems. This work takes a major step towards the verification of all combinations of simultaneous exceptions in processors.