Effect of post-metallization anneal on monolithic co-integration of Hf0.5Zr0.5O2-based FeFET and CMOS

Hafnium oxide-based ferroelectrics, particularly zirconium-doped HfO<sub>2</sub> (HZO), have demonstrated excellent compatibility with CMOS fabrication processes. However, the impact of post-metallization annealing (PMA)-a key step in optimizing device performance-on CMOS and FeFET co-integrated devices has yet to be fully explored. This study investigates the effects of PMA under N<sub>2</sub> and H<sub>2</sub> ambients on the electrical properties of pMOSFET and nFeFET devices monolithically co-integrated on an 8-inch wafer. N<sub>2</sub> annealing leads to a significantly larger memory window in FeFETs, attributed to enhanced crystallinity and reduced oxide-trapped charges. In contrast, while H<sub>2</sub> annealing is less effective in improving ferroelectric properties, it markedly lowers the interface trap density (D<sub>it</sub>) in both CMOS and FeFET devices. This reduction in D<sub>it</sub> leads to improved SS, as reflected in the higher gain observed in FeFET-based co-integrated inverters. These findings offer valuable insights for optimizing PMA conditions based on the performance requirements for co-integrated FeFET and CMOS devices.

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Publication Details

Journal
Scientific Reports
Published
2025-05-18
DOI
https://doi.org/10.1038/s41598-025-02281-8
Citations
3
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
2.19

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article

Effect of post-metallization anneal on monolithic co-integration of Hf0.5Zr0.5O2-based FeFET and CMOS

Bohyeon Kang, Sung–Min Ahn, Rock‐Hyun Baek, Jehyun An et al.
3 citations
Scientific Reports
Ferroelectric and Negative Capacitance Devices
2.19
article

Effect of post-metallization anneal on monolithic co-integration of Hf0.5Zr0.5O2-based FeFET and CMOS

Bohyeon Kang, Sung–Min Ahn, Rock‐Hyun Baek, Jehyun An, Giryun Hong, Jongseo Park, Beomjoo Ham, Jaeseong Pyo
article en
3 citations

Abstract

Hafnium oxide-based ferroelectrics, particularly zirconium-doped HfO<sub>2</sub> (HZO), have demonstrated excellent compatibility with CMOS fabrication processes. However, the impact of post-metallization annealing (PMA)-a key step in optimizing device performance-on CMOS and FeFET co-integrated devices has yet to be fully explored. This study investigates the effects of PMA under N<sub>2</sub> and H<sub>2</sub> ambients on the electrical properties of pMOSFET and nFeFET devices monolithically co-integrated on an 8-inch wafer. N<sub>2</sub> annealing leads to a significantly larger memory window in FeFETs, attributed to enhanced crystallinity and reduced oxide-trapped charges. In contrast, while H<sub>2</sub> annealing is less effective in improving ferroelectric properties, it markedly lowers the interface trap density (D<sub>it</sub>) in both CMOS and FeFET devices. This reduction in D<sub>it</sub> leads to improved SS, as reflected in the higher gain observed in FeFET-based co-integrated inverters. These findings offer valuable insights for optimizing PMA conditions based on the performance requirements for co-integrated FeFET and CMOS devices.

Scientific ReportsVol. 15(1)
Pohang University of Science and Technology (KR)
National Research Foundation, Ministry of Trade, Industry and Energy, National Research Foundation of Korea, Ministry of Science and ICT, South Korea
Openalex Percentile: Top 12%
Ferroelectric and Negative Capacitance Devices
2.19
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