DESIGN AND PERFORMANCE ANALYSIS OF 12T SRAM FOR LOW POWER APPLICATIONS

Memory design approaches primarily prioritise the reduction of memory power usage, which is often achieved via innovative use of caching to save power utilisation.Power consumption of an external memory access typically much more compared to that of on-chip accessibility, by at least ten times.This research investigates the influence of process variables on several design metrics, including the reading and writing power and current of the proposed cell.These attributes are juxtaposed with a previously designed SRAM cell.The simulation results for reading and writing power consumption include all potential process corners, voltage variations, and temperature swings.The proposed SRAM-12T design decreases read power consumption by 60% relative to the existing architecture.Reduced PVT variability among these components lowers FinFET leakage power.The reduction in threshold potential has heightened sub-threshold current leakage, leading to significant static leakage power.The suggested architecture optimises SRAM cell pairings for speed and power efficiency.Enhancements in FinFET-based 12T SRAM cells provide heightened efficiency.The proposed device consumes 15% less power than conventional SRAM cells.