Residue Amplifier Gain Error Duplication and Cancellation for Two-Step Pipelined ADCs

This article proposes Error Duplication and Cancellation (EDC) to tolerate the residue amplifier (RA) gain error in pipelined ADCs. EDC cancels the gain error of the RA by virtue of duplicating and subtracting the gain error in the analog domain, thus avoiding additional digital calibration circuitry and loops. EDC also obviates the need of a high-gain op amp and additional timing phases. Behavioral simulations of a 300-MHz, 12-bit two-step pipelined successive-approximationregister (SAR) ADC show EDC maintains a stable signal-to-noise-and-distortion ratio (SNDR) over RA gain errors as large as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 30$</tex>%, and improves the SNDR by nearly 7.2 dB with a 20% gain error. EDC improves the yield of the ADC from 47.3% to 98.9% over 1,000 runs of RA gain variations.