Role of Dielectric-Semiconductor Interface Traps in Multilayer MoS₂ FinFETs: An Investigation From Device to Circuit

The potential of multilayer MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FinFETs for next-generation electronics has garnered significant attention, making it imperative to examine the effect of dielectric-semiconductor interface traps on their digital and analog/RF performance. Therefore, in this study, the impact of acceptor and donor interface traps on the device characteristics is systematically investigated using the self-consistence solutions of poisson’s and NEGF with SRH trap model. The investigation primarily focuses on: (a) Variation in donor and acceptor dielectric-semiconductor interface trap concentrations (Dit) from 1×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> to 1×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup>, (b) Examining temperature effects from 100 K to 400 K for both trap types, and (c) implementing a Common Source (CS) amplifier. The findings revealed that increasing the concentration of acceptor traps significantly impacts the digital (~97.63% ↓ in I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub>), analog (~92.16% ↓ in g<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub>), RF (~9.5× ↓ in f<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub>) performance of the device, whereas donor traps produce negligible changes, leaving the device performance largely unaffected. Further, the adoption of lower temperatures, even in the presence of both trap cases, enables performance enhancement in digital characteristics with I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub>/I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> improved from 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> to 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">27</sup> (10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> to 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sup>) for acceptor (donor) traps. The analog/RF metrics such as A<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> [~44.35dB – ~59.43dB (~40.28dB – ~48.82dB) for acceptor (donor)] and fT [~24.04GHz – ~39.5GHz (~40.6GHz – ~72.1GHz) for acceptor(donor)] displayed a significant boost, making multilayer MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FinFETs suitable for space and nuclear applications. Moreover, the CS amplifier incorporating donor traps demonstrates an improvement in gain by ~32.3% over the acceptor traps case. Overall, this study highlights the critical role of dielectric-semiconductor interface traps, particularly acceptor traps, in shaping the performance of multilayer MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FinFETs where performance reliability is paramount.