FPGA Based Artificial Neural Network Accelerator

In modern applications, Convolutional Neural Networks (CNNs) are popular for their adaptability and high classification accuracy. Field-Programmable Gate Arrays (FPGAs) are considered suitable platforms for CNNs due to their quick development and configurability. To optimize CNN accelerators, research focuses on network designs, data formats, and FPGA resource utilization. Recent studies explore low-precision data types through quantization to enhance speed and resource efficiency without significant accuracy loss. Network design optimization enhances resource utilization, parallelization for reduced latency, and increased memory access bandwidth. This study investigates a fixed-point data type-based CNN accelerator with multiple approximation accumulation units. It applies the LeNet-5 CNN architecture to classify the MNIST handwritten digit dataset and employs a high-level synthesis tool to create the accelerator on a Xilinx FPGA.