A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure

The wafer-on-wafer (WoW) stacked structure exhibits pioneering advantages in near-memory computing but encounters challenges in 3D analysis due to the miniaturization of vertical connection structures and the simplification of vertical drivers. This article introduces a 3D unified analysis method (3D-UAM), which facilitates standard-cell-level signal integrity (SI) analysis across the 3D WoW stacked structure with hybrid processes, including a comprehensive 3D vertical connection theoretical model that bridges the dynamic random access memory (DRAM) and logic netlists. The accuracy of the 3D-UAM is confirmed through consistency analysis with the results of the 3D field model. The authenticity of the 3D-UAM is validated through correlation analysis with the physical test results from the WoW stacked DRAM test chip. The practicality of the 3D-UAM is demonstrated through channel optimization on a 20-layer DRAM WoW structure and power integrity (PI) analysis for the WoW stacked structure.

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Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2025-05-16
DOI
https://doi.org/10.1109/tvlsi.2025.3566468
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure

Fujun Bai, Jie Tan, Xiaodong Long, Fenning Liu et al.
4 links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D IC and TSV technologies
article

A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure

Fujun Bai, Jie Tan, Xiaodong Long, Fenning Liu, Liang Bai, Yixin Guo, Yong Han, Tao Wei, Xuerong Jia, Jin Li, Jing Liu, Song Chen, Qi Liu, Song Wang, Yubing Wang, Xiping Jiang, Peng Yin, Fuzhi Guo, Zhongcheng Yu, M. D. Cheng
article en

Abstract

The wafer-on-wafer (WoW) stacked structure exhibits pioneering advantages in near-memory computing but encounters challenges in 3D analysis due to the miniaturization of vertical connection structures and the simplification of vertical drivers. This article introduces a 3D unified analysis method (3D-UAM), which facilitates standard-cell-level signal integrity (SI) analysis across the 3D WoW stacked structure with hybrid processes, including a comprehensive 3D vertical connection theoretical model that bridges the dynamic random access memory (DRAM) and logic netlists. The accuracy of the 3D-UAM is confirmed through consistency analysis with the results of the 3D field model. The authenticity of the 3D-UAM is validated through correlation analysis with the physical test results from the WoW stacked DRAM test chip. The practicality of the 3D-UAM is demonstrated through channel optimization on a 20-layer DRAM WoW structure and power integrity (PI) analysis for the WoW stacked structure.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 33(8)
University of Science and Technology of China (CN), Xi'an UniIC Semiconductors (China) (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 91%
3D IC and TSV technologies
DOISourceOpenAlex
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