Surface Reconstruction for Enhancing the Overlay Modeling Optimization Procedure in Photolithography Processes

In the photolithography process of integrated circuit (IC) manufacturing, overlay (OL) control is a key factor for successful exposure. Overlay control is achieved by creating models that can estimate the expected overlay error, so that this can be corrected before the wavefront reaches the wafer surface. Such models consist of basis functions, influenced by application-controllable variables such as process settings, tool characteristics, and field-related factors with their corresponding model parameters. The process of tuning the model parameters involves several time-consuming sensor measurements on markers distributed across the wafer surface and significantly impacts the throughput performance of the exposure system. For this reason, a strategic selection of wafer markers is necessary. In this paper, we propose a methodology to improve the overlay modeling process by exploiting Surface Reconstruction (SR). SR is used as an intermediate step, during the parameter estimation process, to generate additional data from a strategically selected set of markers that are spatially uniform and provide maximum information gain. The proposed method reconstructs the wafer surface by incorporating spatially interpolated estimates derived from the physical insights of existing measurements. This augmented data set, comprised of measured and synthetic overlay data, serves as a comprehensive input for the parameters’ tuning process leading to more accurate overlay modeling. The proposed method is evaluated using real-industry data from a semiconductor process of 300mm diameter wafers. The results demonstrate a significant reduction in the overlay residuals in both x and y directions.

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Publication Details

Journal
IEEE Transactions on Semiconductor Manufacturing
Published
2025-05-16
DOI
https://doi.org/10.1109/tsm.2025.3570904
Citations
2
Primary Topic
Advancements in Photolithography Techniques
Type
article
Field-Weighted Citation Impact
1.46
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article

Surface Reconstruction for Enhancing the Overlay Modeling Optimization Procedure in Photolithography Processes

Aris Magklaras, Sadri Güler, Christos Gogos, Panayiotis Alefragis et al.
2 citations
IEEE Transactions on Semiconductor Manufacturing
Advancements in Photolithography Techniques
1.46
article

Surface Reconstruction for Enhancing the Overlay Modeling Optimization Procedure in Photolithography Processes

Aris Magklaras, Sadri Güler, Christos Gogos, Panayiotis Alefragis, Alexios Birbas
article en
2 citations

Abstract

In the photolithography process of integrated circuit (IC) manufacturing, overlay (OL) control is a key factor for successful exposure. Overlay control is achieved by creating models that can estimate the expected overlay error, so that this can be corrected before the wavefront reaches the wafer surface. Such models consist of basis functions, influenced by application-controllable variables such as process settings, tool characteristics, and field-related factors with their corresponding model parameters. The process of tuning the model parameters involves several time-consuming sensor measurements on markers distributed across the wafer surface and significantly impacts the throughput performance of the exposure system. For this reason, a strategic selection of wafer markers is necessary. In this paper, we propose a methodology to improve the overlay modeling process by exploiting Surface Reconstruction (SR). SR is used as an intermediate step, during the parameter estimation process, to generate additional data from a strategically selected set of markers that are spatially uniform and provide maximum information gain. The proposed method reconstructs the wafer surface by incorporating spatially interpolated estimates derived from the physical insights of existing measurements. This augmented data set, comprised of measured and synthetic overlay data, serves as a comprehensive input for the parameters’ tuning process leading to more accurate overlay modeling. The proposed method is evaluated using real-industry data from a semiconductor process of 300mm diameter wafers. The results demonstrate a significant reduction in the overlay residuals in both x and y directions.

IEEE Transactions on Semiconductor ManufacturingVol. 38(3)
University of Peloponnese (GR), University of Patras (GR), University of Ioannina (GR), ASML (Netherlands) (NL)
Openalex Percentile: Top 17%
Advancements in Photolithography Techniques
1.46
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