Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs

• A novel Multi-Step Package for series-connected SiC-MOSFETs has been analyzed in this work. • The parasitic capacitances of gate drive circuits and package geometries significantly influence voltage sharing performance of series-connected SiC-MOSFETs. • Voltage imbalance can be substantially reduced by optimizing the design of package geometries. • The effects of gate drive parasitic capacitances on voltage sharing can be mitigated through the compensating influence of packaging parasitic capacitances. This paper analyzes a novel packaging technique to improve the voltage-sharing performances of series-connected SiC-MOSFETs. The proposed method takes advantage of the parasitic capacitance network introduced by the packaging dielectric isolation layers to reduce the voltage imbalance across the series-connected devices. Firstly, the study carried out in this work explains how the parasitic capacitance networks introduced by the classic planar packaging and the gate drive circuits cause voltage imbalances across the devices. Therefore, a new packaging concept is analyzed to compensate for the effects of the gate driver parasitic capacitances. The concept is introduced and analyzed using equivalent models and mathematical approaches. To verify the analysis, the voltage sharing between two series-connected 1.2 kV SiC-MOSFETs is tested in a pulse test setup. The experimental results confirm that the proposed voltage-balancing technique can drastically improve the voltage-sharing performance of series-connected devices.