A 62.54 nW Carbon–Silicon Heterogeneous-Integrated SRAM with Novel Low-Power Memory Cell

As a critical component of computer systems, static random access memory (SRAM) plays a significant role in the fields of high-performance computing, artificial intelligence, and the Internet of Things. However, the conventional silicon-based SRAM is facing problems such as high power consumption, integration limitations, and the need for performance improvement. For the power consumption challenge of SRAM, a novel read/write-decoupled SRAM cell is proposed in this paper. When SRAM is in a standby state, utilization of this cell can effectively reduce the leakage current, thereby reducing the static power consumption. In addition, a novel carbon–silicon heterogeneous-integrated SRAM technology is proposed in this paper. The carbon–silicon heterogeneous-integrated SRAM technology combines the high mobility, low power consumption, and low temperature process compatibility of carbon nanotubes (CNTs) with mature silicon-based fabrication processes, enabling significant optimization of access time and power consumption. The SRAM was implemented by a silicon-based 55 nm process and a carbon-based 500 nm process. The simulation results showed that when the power supply was 1.2 V, the access time of SRAM with the silicon 55 nm process was 886 ps. The static and dynamic power consumption was 91.51 nW and 1.48 mW, respectively. The SRAM with carbon–silicon heterogeneous-integrated technology achieved an access time of 872 ps, a static power consumption of 62.54 nW, and a dynamic power consumption of 1.07 mW, representing reductions of 1.58%, 31.66%, and 27.70%, respectively.