Instruction serial fusion for power-efficient vector processing

The limitations of traditional Von Neumann architectures in data flow and instruction control have become critical as computational demands grow and energy efficiency becomes imperative, especially in vector processors handling largescale parallel computations. Such systems exhibit significant power overhead due to frequent data transfers between registers and computing units. This paper presents an instruction serial fusion technique that dynamically identifies data dependencies between consecutive instructions and merges multiple operations into a single composite instruction. By reducing redundant data movements between registers and functional units, our method achieves 3.26%-7.98% overall chip power reduction, with 7.93%-17.81% power savings in vector registers. Notably, it eliminates read-after-write (RAW) conflicts without compromising computing unit utilization. We validate our approach through matrix computation benchmarks on the RISC-V vector processor Ara. Power and area evaluations were conducted using Design Compiler. Results show negligible area overhead (+0.3%) and measurable improvements in computing unit efficiency due to RAW conflict resolution. This work demonstrates a promising tradeoff between energy efficiency and performance for next-generation vectorized architectures.