A 6.6‐GHz Dual‐Path Reference‐Sampling PLL With 139.6‐fs RMS Jitter and −75.2‐dBc Spur in 28‐nm CMOS

ABSTRACT This paper presents a dual‐path reference‐sampling phase‐locked loop (RSPLL) with low RMS jitter, low reference spur, and compact area. To suppress the high in‐band phase noise from the G M , an octuple‐sampling phase detector is used to enhance the phase detection gain. To lower the loop filter area in the conventional single‐path type‐II RSPLL, a dual‐path loop architecture is introduced to greatly reduce the integrating capacitor. In addition, by combining a low‐power retimer‐less multi‐modulus divider and clock generator, the overall power efficiency of the RSPLL is improved. The proposed RSPLL is implemented in a 28‐nm CMOS process. With a 100‐MHz input reference, the prototype achieves 139.6‐fs root‐mean‐square (RMS) jitter (1 kHz‐100 MHz), −75.2‐dBc reference spur and −250.5‐dB figures‐of‐merit (FOM).