A Multi-Stage WPDC Optimized Separately for Even and Odd Modes

This paper introduces a compact multi-stage Wilkinson power divider/combiner (WPDC) topology which enables broadband operation with isolation capacitors and requiring only one single isolation resistor. The application of an L network for even-mode impedance matching and a π network for odd-mode impedance matching results in a more compact circuit layout and lower insertion loss compared to conventional WPDC designs. A K- and Ka-band WPDC is designed using a 45RFE process with measurements verifying the proposed topology. The results of a two-stage WPDC show an insertion loss below 0.7 dB, isolation better than 20 dB, and input/output return loss exceeding 12 dB across the frequency range of 18.6 to 33.6 GHz. The corresponding amplitude imbalance is within 0.06 dB, and the phase difference is below 0.8 degrees. The core chip size is 210 μm × 186 μm, which is only 0.018 λ0 × 0.016 λ0 at the center frequency of 26.1 GHz. Thus, this integrated passive component holds significant promise as a viable solution for wideband applications.

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Publication Details

Journal
Electronics
Published
2025-05-15
DOI
https://doi.org/10.3390/electronics14102023
Primary Topic
Particle accelerators and beam dynamics
Type
article
Field-Weighted Citation Impact
0.00

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article

A Multi-Stage WPDC Optimized Separately for Even and Odd Modes

Xudong Wang, Xinyi Zhang, C. K. Yang, Fangkai Wang
Electronics
Particle accelerators and beam dynamics
article

A Multi-Stage WPDC Optimized Separately for Even and Odd Modes

Xudong Wang, Xinyi Zhang, C. K. Yang, Fangkai Wang
article en

Abstract

This paper introduces a compact multi-stage Wilkinson power divider/combiner (WPDC) topology which enables broadband operation with isolation capacitors and requiring only one single isolation resistor. The application of an L network for even-mode impedance matching and a π network for odd-mode impedance matching results in a more compact circuit layout and lower insertion loss compared to conventional WPDC designs. A K- and Ka-band WPDC is designed using a 45RFE process with measurements verifying the proposed topology. The results of a two-stage WPDC show an insertion loss below 0.7 dB, isolation better than 20 dB, and input/output return loss exceeding 12 dB across the frequency range of 18.6 to 33.6 GHz. The corresponding amplitude imbalance is within 0.06 dB, and the phase difference is below 0.8 degrees. The core chip size is 210 μm × 186 μm, which is only 0.018 λ0 × 0.016 λ0 at the center frequency of 26.1 GHz. Thus, this integrated passive component holds significant promise as a viable solution for wideband applications.

ElectronicsVol. 14(10)
Nankai University (CN)
Nankai University, Fundamental Research Funds for the Central Universities
Openalex Percentile: Top 86%
Particle accelerators and beam dynamics
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A Multi-Stage WPDC Optimized Separately for Even and Odd Modes — Xudong Wang, Xinyi Zhang, et al. · Electronics (2025) | TGRS Research Map | TGRS