Asymmetric Reliability and Universality of Defect Formation in Oxide-Gated Ultra-Thin In₂O₃Vertical FETs for Monolithic 3-D Integration

Monolithic 3D integration for back-end-of-line (BEOL) vertical FET is an important emerging technology for the semiconductor industry, because of its high density, high performance, and improved power savings due to the reduced area and shorter interconnects. In this regard, oxide channel transistors are particularly promising because of the ultra-high performance of devices fabricated at low temperatures. In this work, we report the performance, reliability, and reliability implications of the asymmetric oxide-based vertical transistors (ov-FET) with atomic-layer-deposited (ALD) 1.6 nm In 2O3 vertical channel and ALD In2O3 gate electrode. In the flipped bias configuration, the threshold voltage shift (Vth) reduces by 0.14V (40%) and 0.19V (47%), respectively, for positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI). We conclude by developing a universal scaling technique of three defect generation mechanisms of total threshold voltage (Vth) degradation, and use the model to predict PBTI/NBTI ΔVth. for various stress conditions. Our work illustrates that In2O3 vertical transistors are suitable for BEOL 3D integration and create a predictive modeling framework for performance/reliability co-optimization.