Analytical Modeling of RTN with Short Dwell Time for Strict Memory Bit Error Estimation

We derive an analytical model of the average current distribution of random telegraph noise (RTN). This model comprehensively and correctly reproduces experimental current distributions. Moreover, the RTN parameters extracted from experimental data using the proposed model are consistent with those derived by a conventional method. In addition, the average dwell time parameters can be estimated, even when they are shorter than the measurement integration time. Such estimation is difficult using previous methods. Furthermore, the proposed analytical model allows to strictly estimate the RTN-induced memory bit error rates. Hence, this method can be particularly useful for predicting extremely rare bit errors caused by RTN with a very short dwell time.

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Published
2025-03-30
DOI
https://doi.org/10.1109/irps48204.2025.10983764
Primary Topic
Semiconductor materials and devices
Type
article
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article

Analytical Modeling of RTN with Short Dwell Time for Strict Memory Bit Error Estimation

Kenzo Manabe, Kazuya Uejima, Yasuhito Hayashi
Semiconductor materials and devices
article

Analytical Modeling of RTN with Short Dwell Time for Strict Memory Bit Error Estimation

Kenzo Manabe, Kazuya Uejima, Yasuhito Hayashi
article en

Abstract

We derive an analytical model of the average current distribution of random telegraph noise (RTN). This model comprehensively and correctly reproduces experimental current distributions. Moreover, the RTN parameters extracted from experimental data using the proposed model are consistent with those derived by a conventional method. In addition, the average dwell time parameters can be estimated, even when they are shorter than the measurement integration time. Such estimation is difficult using previous methods. Furthermore, the proposed analytical model allows to strictly estimate the RTN-induced memory bit error rates. Hence, this method can be particularly useful for predicting extremely rare bit errors caused by RTN with a very short dwell time.

National Institute of Advanced Industrial Science and Technology (JP)
Openalex Percentile: Top 91%
Semiconductor materials and devices
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Analytical Modeling of RTN with Short Dwell Time for Strict Memory Bit Error Estimation — Kenzo Manabe, Kazuya Uejima, et al. · (2025) | TGRS Research Map | TGRS