Trap Behaviors and Degradation Modeling in Positive Bias Temperature Instability of Back Gated IGZO Transistors
In this paper, the positive bias instability (PBTI) of back-gated IGZO transistors shows two kinds of electron-trapping behaviors: saturation and power-law model. A PBTI model based on two-traps in gate dielectrics of IGZO transistors is proposed, and PBTI results under different temperatures and voltage biases are fitted. A new dynamic physical explanation of the temperature-dependent variation of traps in the gate dielectrics of IGZO transistors under PBTI stress is proposed.
Authors
- Liang Xiang (ORCID: https://orcid.org/0009-0005-3304-2068)
- Yunfei Shi (ORCID: https://orcid.org/0000-0002-5527-1014)
- Gangping Yan (ORCID: https://orcid.org/0000-0002-5364-3224)
- Huaxiang Yin (ORCID: https://orcid.org/0000-0001-8066-6002)
- Hong Yang (ORCID: https://orcid.org/0000-0003-2860-5901)
- Guilei Wang (ORCID: https://orcid.org/0000-0002-1311-8863)
- Shangbo Yang (ORCID: https://orcid.org/0009-0003-1837-393X)
- Xiaolei Wang
- Chao Zhao (ORCID: https://orcid.org/0000-0001-9502-2955)
- Jun Luo (ORCID: https://orcid.org/0000-0002-4136-384X)
- Gaobo Xu (ORCID: https://orcid.org/0000-0001-7177-4132)
Institutions
- Chinese Academy of Sciences (CN)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983617
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00