Understanding Correlation Between Memory Window Closure, Leakage and Read Delay Effects for FEFET Reliability Improvement: Role of IL and FE Traps

Memory window (MW) closure, read delay, and gate leakage are three key reliability challenges in ferroelectric (FE) field-effect transistors (FEFETs), all of which have traditionally been analyzed separately. In this work, we exploit dedicated experiments and device simulations to present a detailed study of these three mechanisms in Si-FEFETs with a 10nm layer of FE HZO. The results reveal critical insights into the interplay between trap generation and polarization switching (PS), and the correlation between MW closure, read delay, and leakage current. First, we show that trap generation is accelerated by PS and initially (up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\times 10^{4}$</tex> cycles) occurs mainly in the interfacial layer (IL). These PS induced traps are slow traps and are found to be responsible for both reduction in MW recovery with read delay and MW closure, demonstrating a strong correlation between the two mechanisms. Finally, we show that leakage current increase is controlled by the generation of HZO traps, which is triggered by internal field redistribution once IL is highly degraded (after MW closure). The engineering of FEFETs to minimize the formation of slow (de)trapping defects in the IL is essential to improve overall reliability of the FEFET device.