Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with Improved Latch-Up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os

In this work, a novel silicon-controlled rectifier (SCR) based local protection concept is presented with co-engineered device and trigger circuit. This results in improved latch-up robustness, lower PAD capacitive loading and lower leakage when compared to the reference (state-of-the-art till date) concept. The proposed and reference concepts are realized in Samsung 28nm process for experimental validation and benchmarking. Its TLP/vf-TLP characteristics and other ESD measurement results along with the design trade-offs are presented and compared with the reference concept. A TCAD based device and circuit co-optimization (DTCO) methodology is also presented. The proposed concept can realize the demanding I/O needs of SCR based local clamps, qualified for HBM to CDM time domains, and meeting ESD specs required for high speed I/O buffers.