Impact of Bi-Layer Gate Stack and Thickness on Low Frequency TDDB in FinFET and Planar Devices

AC TDDB (Time-Dependent-Dielectric-Breakdown) lifetime exhibits inconsistency at low frequencies (<10kHz), while it is reported to be longer at higher frequencies. In this study, AC TDDB mechanism is systematically investigated over a frequency range of 2Hz to 500kHz. Notably, n-type transistors with bi-layer gate stack demonstrate degradation of AC TDDB lifetime below that of DC TDDB in both FinFET and Planar devices. This degradation worsens as the gate oxide thickness decreases, a phenomenon explained by Maxwell-Wagner instability. To mitigate this degradation at low frequencies (LF), applying a small positive voltage during the off-state of the AC pulse (Vr) can improve reliability, particularly in circuits operating at low frequencies.