Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers
This paper explores gate injection layer (GIL) engineering in ferroelectric FET-based Vertical NAND (Fe-VNAND) devices, focusing on enhancing the memory window (MW) through advanced dynamic modeling. By simulating the complex interplay between charge trapping and polarization interactions at the GIL/ferroelectric interface using Sentaurus TCAD, we identify critical factors that influence MW enhancement and degradation. This work provides novel insights and design guidelines for optimizing Fe-Vnandperformance, addressing key challenges that have not been thoroughly explored in prior studies.
Authors
- Kijoon Kim (ORCID: https://orcid.org/0000-0003-2689-8376)
- Daewon Ha (ORCID: https://orcid.org/0000-0002-9061-8626)
- Chinsung Park (ORCID: https://orcid.org/0000-0001-9631-2866)
- Suman Datta (ORCID: https://orcid.org/0000-0001-6044-5173)
- Lance Fernandes (ORCID: https://orcid.org/0009-0000-9896-8842)
- Minji Shon (ORCID: https://orcid.org/0009-0001-5498-037X)
- Asif Islam Khan (ORCID: https://orcid.org/0000-0003-4369-106X)
- Shimeng Yu (ORCID: https://orcid.org/0000-0002-0068-3652)
- Wanki Kim
- Suhwan Lim (ORCID: https://orcid.org/0000-0003-3578-5488)
- Kwangsoo Kim (ORCID: https://orcid.org/0000-0001-8243-3472)
- Prasanna Venkatesan Ravindran
- Jongho Woo
Institutions
- Georgia Institute of Technology (US)
- Samsung (South Korea) (KR)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983663
- Citations
- 2
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 1.46