Positive Bias Temperature Instability in Polysilicon/SiO2 PMOS Transistors for Analog High Precision Applications

In this paper, we study the impact of Positive Bias Temperature Instability (PBTI) driven threshold voltage shift on high precision amplifiers with polysilicon/SiO2 PMOS input transistors. High Temperature Operating Life (HTOL) measurements of high precision amplifier biased in open loop comparator mode showed offset voltage drift driven by PBTI degradation mechanism. We developed a new wafer level test structure that is sensitive to 10μV threshold voltage drift to perform PBTI modeling tests at sub-nominal operating bias conditions relevant for high precision amplifiers. Wafer level modeling tests showed that the PBTI degradation mechanism is modulated by the gate poly doping with p-polysilicon PMOS exhibiting much higher degradation compared to n-polysilicon PMOS. Finally, we demonstrate a BTI tolerant design methodology for high precision amplifiers with PMOS input pair transistors.