Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation

This paper presents ring-oscillator (RO) based experimental study of leakage current fluctuation (▵Leak) on logic circuit due to on-state and off-state stress in 3 nm CMOS process. Measured results show that off-state stress causes leakage increases at high voltage stress. However, it does not have significant impact under normal voltage conditions even in the very fine 3 nm process. As for on-state stress, leakage current is reduced with increasing threshold voltage (Vth) by bias temperature instability (BTI). This improves voltage drop and compensates for performance degradation over time. A block level impact analysis is presented, showing 31% reduction in BTI guard-band.