Application-based Modeling of I/O Reliability
This work presents a novel approach for modeling reliability degradation in a stacked-device input/output (I/O) circuit test structure. A large experimental study was done to generate an empirical model using conventional reliability parameters, circuit settings, and board elements to provide an application-level degradation profile. The approach can be readily applied to other circuits, applications, and parameters.
Authors
- Harold Sanchez
- R. Peng
- Amish J. Patel (ORCID: https://orcid.org/0000-0001-6482-543X)
- Mehul D. Shroff (ORCID: https://orcid.org/0000-0002-7664-8941)
- C. Le Cam
- Juncheng Jiang (ORCID: https://orcid.org/0000-0001-7018-2709)
- Weisheng S. Zhao (ORCID: https://orcid.org/0000-0001-8088-0404)
- G. Liu
- Rongwei Ye (ORCID: https://orcid.org/0000-0003-1744-2668)
- L. Zhang
- Zhiyong Liu (ORCID: https://orcid.org/0000-0002-6958-5233)
- Lu Chen (ORCID: https://orcid.org/0000-0002-5685-7017)
- Ke Xie (ORCID: https://orcid.org/0000-0001-7784-8454)
- David Bearden
- R. Pavlanin
- S. Kala-Janssen
- C. Magnella
- C. Richards-Chacon
- J. Satasia
Institutions
- NXP (Netherlands) (NL)
- ON Semiconductor (China) (CN)
- ON Semiconductor (Czechia) (CZ)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983302
- Primary Topic
- Industrial Vision Systems and Defect Detection
- Type
- article
- Field-Weighted Citation Impact
- 0.00