Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation

We propose a unique Resistive-gate RAM which is scalable to 16nm FinFET generation and beyond. It consists of an 1TnR RRAM array where a 2D prototype is demonstrated and can be readily extended to 3D. Here, vertical RRAMs are integrated directly on FinFET by a backend process to form a memory core. Results demonstrated that this RG-RRAM can operate below 3V. At chip level, read latency as low as 25ns at 1V can be achieved. Reliability tests also showed that the design exhibits excellent immunity to disturbances during SET, RESET, and READ operations, excellent endurance and excellent data retention. With technology scaling, it is expected to be applicable to various generations of FinFET and nanosheet.