Repetitive Short-Circuit Ruggedness of Different SiC MOSFET Channel Designs

This study investigates the repetitive short-circuit ruggedness of the three main SiC MOSFET gate channel designs available in the market: planar, symmetrical, and asymmetrical trench. The devices under test (DUTs) were first analyzed in their pristine state. Then stressed with similar short-circuit energy density. Electrical parameters such as gate-source voltage, drain current, and drain-source voltage were monitored over 1000 short-circuit cycles. Multiple samples from four manufacturers were utilized to build enough statistical significance. After the stress, the DUTs were characterized with a curve tracer, and a few failed DUTs were analyzed in depth to localize via photon emission microscopy (PEM) and understand the type of failure via focused ion beam (FIB). The outcomes showed that planar gate structures were weaker than their trench counterparts and that the gate oxide thickness in planar structures plays a pivotal role in the cycle robustness: the thinner the better. The weakness resulted from the elevated temperature at the gate oxide, caused by the higher specific energy dissipated per unit-channel-width and aggravated by the unfavorable thermal dissipation towards the top side metallization. The conclusions and the root cause of failure were further confirmed via TCAD simulation.