Post-Silicon Validation of Static Lockstep Mode on Intel<sup>®</sup> Xeon<sup>®</sup> Processor E-Core Architecture
Error detection mechanisms are essential to ensure high reliability in data centers. We present a post-silicon validation of Intel's new core lockstep feature based on laser fault injection. Our experimental data shows lockstep is able to mitigate up to 100% of the errors that would otherwise be silent. Keywords-Reliability, Validation, Lockstep, HPC, Laser
Authors
- Bjørn Axel Gran
- Ricardo Ascázubi (ORCID: https://orcid.org/0000-0002-6411-0554)
- F. Libano (ORCID: https://orcid.org/0000-0002-0638-1102)
- S. Mattord
Institutions
- Intel (United States) (US)
Publication Details
- Published
- 2025-03-30
- DOI
- https://doi.org/10.1109/irps48204.2025.10983044
- Citations
- 2
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 1.46