A Study on the Origin of Dynamic Charge Loss of Next Generation DRAM Cell Array Transistor

Dynamic charge loss of next generation DRAM with a cell array transistor consisting of a bulk-less thin body was studied. The relationship between dynamic charge loss and floating body effect during bit line disturbance was shown by experimental and simulation results. It is necessary to minimize both the SN contact GIDL and the BL node contact GIDL in order to manage ‘d0’ and ‘d1’ dynamic operation characteristics simultaneously.