Comprehensive Modeling and Investigation of Intrinsic Variation Source Fluctuation in 2D-Layered Thin Film Transistors

In this work, a Voronoi-TCAD co-simulation framework is developed to investigate the impact of intrinsic and extrinsic variation sources on the performance and variability of 2D-layered TFTs. It is found that : i) High trap density exacerbates device variability by amplifying localized energy barriers and enhancing barrier interference; ii) The device variability reaches peak value for intermediate numbers of grains, while increased numbers of grains reduce overall variability due to statistical averaging effects, highlighting the importance of considering both the quantity of grain boundaries and their spatial distribution as key variability sources; iii) interlayer interactions in multilayer structures further exaggerate the device variability, particularly for the on-current. This demands precise control of grain alignment and distribution. These findings emphasize the importance of grain engineering strategies, such as optimizing grain size, reducing defect density, and improving interlayer uniformity, to suppress variability and enhance device performance in large-scale 2D-layered TFT applications.